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analog/digital mixed asic mixed signal asic mixed signal asic ma-8a, ma-9 family ma-8a, ma-9 family june 2003
nec electronics mixed signal solutions taking on new challenges toward the next generation pamphlet a13326ej2v0pf contents mixed signal applications 3 mixed signal asic product lines 5 ma-8a 8 ma-9 family 21 packages 36
pamphlet a13326ej2v0pf mixed signal applications mixed signal asics enable higher quality and a better cost performance in afe (analog front end) circuits and battery management circuits for applications such as sensors, pc peripheral equipment, and mobile devices. sensors peripheral equipment mobile devices sensor signal control pick-up control servo control light intensity detection auto-focus flash light control battery power control 3
application concept applications dealing with "minute analog signal input in a wide band" require signal amplifi- ers or analog-digital arithmetic circuits (analog front end: afe) for the analog interface. also, for mobile equipment, the need to extend the battery life means an improved power efficiency is essential. nec electronics provides a custom-built battery management ic for cellular phones and other mobile applications. 4 pamphlet a13326ej2v0pf sensor 1 cpu, cell-based ic digital circuit (logic) a/d converter d/a converter analog circuit (amplification) sensor 2 sensor 3 analog signal power mos fet battery charger accessory drive battery vibrator, led, etc. voltage regulator battery management power on/off control efficient battery control afe (analog front end) analog i/f, analog signal processing
5 pamphlet a13326ej2v0pf mixed signal asic product lines nec electronics offers mixed signal asics that employ a bicmos process with a process rule of 0.65 m to 0.35 m. furthermore, the 0.35 m bicmos can incorporate our 0.35 m cell-based ic cb-9 family vx type analog core. 5 v power supply (supports 3.3 v library) 3.3 v power supply for large-scale systems ma-8a ( pd688 ) 0.65 m bicmos process ma-9 family ( pd681 ) 0.35 m bicmos process (equivalent to cb-9vx) logic circuit (gate array configuration) analog circuit (fully customized configuration) logic circuit (cell-based configuration) cell-based ip core analog circuit (fully customized configuration) ?
6 pamphlet a13326ej2v0pf voltage(v) 3.3 5 9 12 42 analog masters digital analog ma-9 family analog circuit (fully customized) analog circuit (fully customized) ma-8a logic circuit logic circuit (equivalent to cb-9vx) a/d, d/a ip core note note a cb-9vx macro can be mounted but not a rom or cpu. mixed signal asic pc5701 pc5702 pc5703 pc5704 pc5023 pc5020 pc5021 pc5022 pc5031 pc5032 pc5734 pc5201 pc5202 pc5203 pc5204 pc5200 0.65 m bicmos process 0.35 m bicmos process integration, function integration mixed signal asic product lines
7 pamphlet a13326ej2v0pf support of small-scale packages in addition to conventional mold packages, various csps (chip size packages) are available to support set downsizing. fpbga tm fplga (fine-pitch bga) (fine-pitch lga)
0.65 m mixed signal asic ma-8a features support of digital/analog mixed circuits by employing the latest bicmos process, the ma-8a realizes the integration of a 0.65 m cmos gate array and analog asic (analog master) on a single chip. analog block element configuration prioritizing circuit functions analog circuits that mix bipolar transistors and cmos transistors can be created through the use of the bicmos process: high input impedance operational amplifiers sample and hold circuits analog switches, etc. simple design and short development time the logic block can be easily developed with opencad tm (nec electronics original cae tool). furthermore, a short development time can be achieved, which is another advantage of asics. 8 pamphlet a13326ej2v0pf
ma-8a application fields the ma-8a can be used to integrate analog/digital mixed circuits applied to multimedia and various other fields on one chip. 9 pamphlet a13326ej2v0pf pc peripheral equipment dscs, single-lens reflex cameras flash light control, zoom lens control storage equipment servo controller lcd panels (active matrix) grayscale power supply controller mobile devices (battery management/speaker drive) cellular phones (pdc, phs, cdma, gsm, gprs) pdas portable game equipment sensor modules geomagnetic sensors (cellular phone gps, etc.) gyro sensors (compensating for hand-shake in dsc, dvc) magnetic sensors (dc motor control, etc.)
ma-8a ma-8a application examples pamphlet a13326ej2v0pf cellular phones (battery management) speaker microphone rf interface power mos fet li-ion battery charger accessory drive sw li-ion battery vibrator, led, etc. ldo voltage regulator base band, cpu ldo voltage regulator ldo voltage regulator 10
ma-8a pamphlet a13326ej2v0pf digital still cameras, single lens reflex cameras (zoom lens control) oscillator logic circuit dc motor crystal resonator temperature and other detectors dc motor encoder circuit comparison amplification impedance conversion as many as there are motors reference voltage adjustment 11
ma-8a 12 pamphlet a13326ej2v0pf chip configuration the ma-8a is mainly composed of a logic circuit (gate array block) and an analog circuit. the i/o cells for the digital/analog interface perform input/output of digital signals between the logic circuit and the analog circuit. i/o cells for digital/analog interface analog circuit test switching pin logic circuit internal cell area test pins logic circuit test switching pin i/o cell for digital/ analog interface digital signals analog circuit internal cell area pamphlet a13326ej2v0pf digital circuit pad analog circuit i/o cell for digital/analog interface analog circuit pad logic circuit internal cell area i/o cell internal cell
ma-8a 13 pamphlet a13326ej2v0pf basic specifications 5.0 v 0.5 v part number process supply voltage f t = 10 ghz, h fe = 80 (all typ.) f t = 10 mhz, h fe = 70 (all typ.) transistors n-ch type, p-ch type for analog circuit npn type pnp type (lateral) mos absolute precision: 20%, relative precision: 2% (all max.) absolute precision: 15%, relative precision: 2% (all max.) polysilicon resistor note capacitor (mos type) note pd688 ?? 0.65 m bicmos process note values indicated are for reference only. the relative precision applies only to when the element is positioned in an adjacent l ocation. pd688 ?? 0.65 m bicmos process 5.0 v 0.5 v (i/o block, internal gates) part number process supply voltage cmos, ttl interface level 190 ps (typ.) 340 ps (typ.) delay time 2.13 ns (typ.) internal gates note 1 input buffer note 2 output buffer note 3 notes 1. value assuming 2-input nand power gate, fan-out 1, and wiring length 0.6 mm/1 pin pair. 2. value assuming fan-out 2, wiring length 0.6 mm/1 pin pair. 3. value assuming load capacitance 15 pf, block name fo01. remark the logic circuit characteristics are the same as those of nec electronics' cmos-8 family. logic circuit analog circuit
ma-8a 14 pamphlet a13326ej2v0pf electrical specifications absolute maximum ratings symbol item meaning v dd supply voltage the range of voltage that, if applied to the v dd pin, will not cause destruction or lower reliability. v i input voltage the range of voltage that, if applied to the input pin, will not cause destruction or lower reliability. v o output voltage the range of voltage that, if applied to the output pin, will not cause destruction or lower reliability. i i input current the absolute value of current capacity that, if applied to the input pin, will not cause latchup to occur. i o output current the absolute value of dc current capacity that, if output from or input to the output pin, will not cause destruction or lower reliability. t a operating ambient temperature range of ambient temperature in which normal logical operation will occur. t stg storage temperature range of pin temperature that will not cause destruction or lower reliability when voltage and current are not applied. definition of absolute maximum rating terms item symbol conditions ratings unit supply voltage v dd ,v cc ? 0.5 to +6.0 v input/output voltage (logic circuit) v i / v o ? 0.5 to v dd + 0.5 v input current (logic circuit) i i 20 ma output current (logic circuit) i o i ol = 3 ma 10 ma i ol = 6 ma 15 ma i ol = 9 ma 20 ma i ol = 12 ma 30 ma i ol = 18 ma 40 ma i ol = 24 ma 60 ma operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
ma-8a 15 pamphlet a13326ej2v0pf recommended operating range (logic circuit) symbol conditions unit max typ min item v dd v 5.5 5.0 4.5 supply voltage v ih v v dd 0.7v dd high-level input voltage v il v 0.3v dd 0 low-level input voltage v p cmos interface v 4.00 1.80 positive trigger voltage v n v 3.10 0.60 negative trigger voltage v h v 1.50 0.30 hysteresis voltage v ih v v dd 2.29 high-level input voltage v il v 0.77 0 low-level input voltage v p ttl interface v 2.54 1.15 positive trigger voltage v n v 1.85 0.59 negative trigger voltage v h v 1.50 0.27 hysteresis voltage t ri ns 200 0 input rise time t fi normal input ns 200 0 input fall time t ri ms 10 0 input rise time t fi schmitt input note ms 10 0 input fall time note do not use this for the clock signal. remark if a signal with a long rise/fall time is input, use a schmitt trigger input buffer to prevent malfunction due to noise superimposed on the signal line. fluctuation of power caused by simultaneous operation of output buffers lowers the capability of the schmitt trigger input buffer, and therefore, care must be exercised in laying out the pins. standard specification cmos interface conditions v dd = 5 v 10%, t a = ? 40 to +85 c (t j = ? 40 to +125 c)
ma-8a 16 pamphlet a13326ej2v0pf standard specification ttl interface conditions v dd = 5 v 10%, t a = 0 to +70 c (t j = 0 to +100 c) symbol conditions min typ max unit v dd 4.5 5.0 5.5 v item supply voltage v ih 0.7v dd v dd v high-level input voltage v il 0.0 0.3v dd v low-level input voltage v p cmos interface 1.90 4.00 v positive trigger voltage v n 0.63 3.10 v negative trigger voltage v h 0.31 1.50 v hysteresis voltage v ih 2.20 v dd v high-level input voltage v il 0.0 0.8 v low-level input voltage v p ttl interface 1.20 2.40 v positive trigger voltage v n 0.60 1.80 v negative trigger voltage v h 0.30 1.50 v hysteresis voltage t ri 0 200 ns input rise time t fi normal input 0 200 ns input fall time t ri 010ms input rise time t fi schmitt input note 010ms input fall time note do not use this for the clock signal. remark if a signal with a long rise/fall time is input, use a schmitt trigger input buffer to prevent malfunction due to noise superimposed on the signal line. fluctuation of power caused by simultaneous operation of output buffers lowers the capability of the schmitt trigger input buffer, and therefore, care must be exercised in laying out the pins.
ma-8a 17 pamphlet a13326ej2v0pf ma-8a development procedure development of the ma-8a is carried out by both the user and nec electronics by divid- ing the work between gate array design using the design resources of the user and circuit design applying nec electronics analog asic technology, which results in a shorter de- velopment time. the transition of development work between the user and nec electronics is called interfacing. the interface level depends on how far the user carries out development work and what data the user provides to nec electronics. circuit diagram level interface in this development method, the user takes care of system circuit design, and the subsequent lsi circuit design and simulation are performed by nec electronics. simulation level interface in this development method, the user is in charge of development from circuit design to simulation using engineering workstations (ews) and cad system simulation tools, and nec electronics is responsible for the rest of the development work. the ma-8a is divided into a logic circuit and an analog circuit, and two kinds of development methods combining the above-described interface levels are available. system circuit design lsi circuit design development method layout design circuit synthesis es production (user side) (nec electronics side) [logic circuit] simulation level interface [analog circuit] circuit diagram level interface [logic circuit] circuit diagram level interface [analog circuit] circuit diagram level interface 1 2
ma-8a 18 pamphlet a13326ej2v0pf logic circuit: simulation level interface analog circuit: circuit diagram level interface user nec electronics development support analog circuit interface analog circuit: circuit design, simulation i/o buffer block design for digital/analog interface circuit connection synthesis analog circuit: placement and routing logic circuit: placement and routing mask production, es production preparation of product specifications cs production mp production determination of desired system specifications system circuit design simulation result verification confirmation of provisional specifications confirmation logic circuit: logic design and circuit design simulation and creation of test pattern es evaluation confirmation confirmation verification of product specifications cs evaluation delivery circuit specification adjustment 1
ma-8a 19 pamphlet a13326ej2v0pf logic circuit: circuit diagram level interface analog circuit: circuit diagram level interface user nec electronics circuit specification adjustment development support analog circuit interface analog circuit: circuit design, simulation design of i/o buffer block for digital/analog interface simulation creation of test pattern circuit connection synthesis analog circuit: placement and routing logic circuit: placement and routing mask production, es production preparation of product specifications cs production mp production determination of desired system specifications system circuit design simulation result verification confirmation of provisional specifications confirmation logic circuit: logic design and circuit design es evaluation confirmation confirmation verification of product specifications cs evaluation delivery 2
ma-8a 20 pamphlet a13326ej2v0pf ma-8a development tools the ma-8a provides development tools that support asic development by the user for the logic circuits. nec electronics will take charge of circuit design for the analog circuits according to the user's specifications. caution a pin should be drawn out as a test pin where the analog circuit is connected to the logic circuit. configure the area where the analog circuit is connected to the logic circuit, as well as the test circuit of the logic circuit in the test circuit block. (gate array block) (test circuit block) analog circuit designed by user or nec electronics opencad (nec electronics' original cae tool) designed by nec electronics logic circuit
0.35 m mixed signal asic ma-9 family features the ma-9 family ( pd681 ?? ) consists of mixed signal asics that aim for system-on- a-chip through the use of a leading-edge 0.35 m bicmos process pioneered by nec electronics. support of analog ip core the ma-9 family can utilize analog circuit design resources such as the a/d converter and d/a converter of nec electronics 0.35 m cell-based ic. leading-edge bicmos process high-speed digital circuits and high-accuracy, sophisticated analog circuits can now be realized on a single chip by employing nec electronics leading-edge 0.35 m bicmos process. low power consumption a low power consumption is achieved for lsis by employing a low-voltage operation process (3.3 v). flexible mixed signal development environment nec electronics development environment for the cb-9 family vx type cell-based ic can be used for the internal logic. pamphlet a13326ej2v0pf 21
22 pamphlet a13326ej2v0pf application fields since cb-9 and later submicron cell-based ics cannot configure an analog circuit, they may not support cb solutions. furthermore, if they incorporate an a/d converter and d/a converter, a good cost performance is not possible due to the restrictions on cell-based ic allocation. in these cases, by integrating the entire cell-based ic, or the a/d converter, d/a converter, and analog circuit blocks on a single chip, the ma-9 family provides the user with the best solution. ma-9 family storage equipment servo/write control dvd-rom/ram drives cd-r/w drives pc peripheral terminals analog front end (a/d converter, d/a converter, analog circuit) sensor signal amplification color lcd panels printers pdas sensor modules geomagnetic sensors (cellular phone gps, etc.) gyro sensors (compensating for hand-shake in dsc, dvc) magnetic sensors (dc motor control, etc.)
ma-9 family 23 pamphlet a13326ej2v0pf analog front end for pc peripherals (printer, tablet) pseudo sine wave 8-bit d/a converter 8-bit d/a converter logic circuit 8-bit a/d converter reference power supply power supply monitor circuit reset circuit series regulator (for cell-based ic) cell-based ic or cpu core v dd control signal external load driving analog signal input analog signal ma-9 family application examples
ma-9 family 24 pamphlet a13326ej2v0pf gyro sensor/magnetic sensor (1/2) (sensor signal amplification + a/d conversion) sensor 1 cpu eeprom tm digital circuit 12-bit a/d converter 10-bit d/a converter 10-bit d/a converter analog circuit sensor 2 sensor 3
ma-9 family 25 pamphlet a13326ej2v0pf gyro sensor/magnetic sensor (2/2) (sensor signal amplification + a/d conversion) cpu logic circuit a/d converter analog circuit (amplification) d/a converter sensor n in y in common n in y in common r x control signal amplification/gain adjustment
ma-9 family chip configuration 26 pamphlet a13326ej2v0pf cb-9vx analog ip core test circuit analog-logic i/f test circuit logic circuit analog circuit user logic (logic gates) a/d or d/a converter macro (cb-9 family vx type) note test circuit test circuit including analog-logic i/f block note neither a cpu nor rom can be mounted. configured by operational amplifier, comparator, reference power supply, analog switch, etc. nec electronics designs the circuit according to the user's circuit specifications. logic circuit analog circuit
ma-9 family 27 pamphlet a13326ej2v0pf basic specifications logic circuit analog circuit part number process supply voltage 3.3 v 0.3 v (i/o block, internal gates) maximum integration (logic only) 1.7 million gates (usable) interface level lvttl internal gates note 1 114 ps (typ.) input buffer note 2 delay time 169 ps (typ.) output buffer note 3 864 ps (typ.) pd681 ?? 0.35 m bicmos process notes 1. value assuming 2-input nand power gate, fan-out 2, and standard wiring length. 2. value assuming fan-out 2 and standard wiring length. 3. value assuming load capacitance 15 pf, i ol = 18 ma. remark the logic circuit characteristics are the same as those of nec electronics' cb-9 family. note values indicated are for reference only. the relative precision applies only to when the element is positioned in an adjacent l ocation. part number process 0.35 m bicmos process supply voltage 3.3 v 0.3 v npn type pnp type (vertical type) f t = 10 ghz, h fe = 70 (all typ.) transistors f t = 2 ghz, h fe = 30 (all typ.) mos n-ch type, p-ch type for analog circuit polysilicon resistor note absolute precision: 20%, relative precision: 2% capacitor (mim type) note absolute precision: 20%, relative precision: 2% pd681 ??
ma-9 family 28 pamphlet a13326ej2v0pf number of steps and usable gates step number number of usable gates vx type 3-layer wiring 2-layer wiring b60 89,600 131,800 c02 117,700 174,200 c40 142,000 211,500 c78 176,100 264,200 d01 195,700 293,600 d26 215,900 326,200 d52 242,200 365,900 d90 277,900 422,900 e16 308,300 469,200 e54 344,200 535,400 e80 373,300 572,400 f18 412,800 647,300 f44 448,300 703,000 f70 479,800 741,500 g08 521,600 824,900 g34 554,300 876,600 g72 612,600 954,500 h10 655,600 1,045,900 h49 714,700 1,140,200 h87 775,400 1,218,600 j26 813,300 1,309,300 j51 855,900 1,377,800 k15 968,800 1,536,000 k92 1,071,600 1,741,400 remark the number of usable gates is calculated using 2-input nand gate conversion. moreover, the above-indicated number of usable gates depends on the megafunctions that are provided and the logic use efficiency, and should therefore be treated as a reference value. remark the number of steps and number of usable gates given for the ma-9 family indicate the size of the entire internal logic including the mixed signal core. = number of steps (number of usable gates) cb-9vx analog ip core test circuit analog-logic i/f test circuit logic circuit analog circuit
ma-9 family number of steps and usable gates 29 pamphlet a13326ej2v0pf absolute maximum ratings item symbol conditions rating unit supply voltage v dd 3.3 v ? 0.5 to +4.6 v i/o voltage v i /v o lvttl buffer v i /v o < v dd + 0.5 v ? 0.5 to +4.6 v output current i o i ol = 1 ma 3 ma i ol = 2 ma 7 ma i ol = 3 ma 10 ma i ol = 6 ma 20 ma i ol = 9 ma 30 ma i ol = 12 ma 40 ma i ol = 18 ma 60 ma i ol = 24 ma 75 ma operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. symbol meaning item v dd the range of voltage that, if applied to the v dd pin, will not cause destruction or lower reliability. supply voltage v i the range of voltage that, if applied to the input pin, will not cause destruction or lower reliability. input voltage v o the range of voltage that, if applied to the output pin, will not cause destruction or lower reliability. output voltage i i the absolute value of current capacity that, if applied to the input pin, will not cause latchup to occur. input current i o the absolute value of dc current capacity that, if output from or input to the output pin, will not cause destruction or lower reliability. output current t a range of ambient temperature in which normal logical operation will occur. operating ambient temperature t stg range of pin temperature that will not cause destruction or lower reliability when voltage and current are not applied. storage temperature definition of absolute maximum rating terms electrical specifications
ma-9 family 30 pamphlet a13326ej2v0pf recommended operating range item symbol conditions min typ max unit supply voltage v dd 3.3 v power supply 3.0 3.3 3.6 v negative trigger voltage v n lvttl buffer 0.6 1.8 v positive trigger voltage v p lvttl buffer 1.2 2.4 v hysteresis voltage v h lvttl buffer 0.3 1.5 v low-level input voltage v il lvttl buffer 0 0.8 v high-level input voltage v ih lvttl buffer 2.0 v dd v input rise time t ri normal input 0 200 ns input fall time t fi 0 200 ns input rise time t ri schmitt input 0 10 ms input fall time t fi 010ms remark the logic circuit characteristics are the same as those of nec electronics' cb-9 family.
ma-9 family 31 pamphlet a13326ej2v0pf analog ip core a/d converter d/a converter remark t a = ? 40 to + 85 c core name power consumption (max.) differential linearity error (max.) 18.0 mw 18.0 mw 20.2 mw 504 mw 28.8 mw 108 mw 1.0lsb 1.0lsb 1.0lsb 1.0lsb 1.0lsb 1.0lsb (typ.) integral linearity error (max.) 1.5lsb 1.5lsb 4.0lsb 2.0lsb 2.0lsb 1.0lsb (typ.) circuit type successive approximation successive approximation successive approximation flash successive approximation sub-ranging operating power supply voltage 2.7 to 3.6 v 3.0 to 3.6 v 2.7 to 3.6 v 3.0 to 3.6 v 3.3 v (typ.) 3.0 to 3.6 v 10 bit-100 khz-1ch 10 bit-100 khz-8ch_mpx 12 bit-300 khz-4ch_mpx 6 bit-70 mhz 8 bit-200 khz-1ch 8 bit-200 khz-8ch 8 bit-50 mhz 8 bit-8 mhz core name power consumption (max.) differential linearity error (max.) 3.6 mw 374 mw 90 mw 180 mw 266.4 mw 7.2 mw 90 mw 180 mw t.b.d. 1.0lsb 1.0lsb 0.5lsb 0.5lsb 0.5lsb 1.0lsb 0.5lsb 0.5lsb 1.0lsb integral linearity error (max.) 1.0lsb 1.5lsb 2.25lsb 2.25lsb 2.25lsb 1.0lsb 1.0lsb 1.0lsb 3.0lsb circuit type resistor string resistor string resistor string resistor string resistor string resistor string resistor string resistor string resistor string operating power supply voltage 3.3 v (typ.) 3.0 to 3.6 v 3.0 to 3.6 v 3.0 to 3.6 v 3.0 to 3.6 v 3.3 v (typ.) 3.0 to 3.6 v 3.0 to 3.6 v under development (v o = 0.75 v) 10 bit-100 khz-1ch 10 bit-135 khz-1ch 10 bit-30 mhz-1ch 10 bit-30 mhz-2ch 10 bit-30 mhz-3ch 8 bit-200 khz-1ch 8 bit-30 mhz-1ch 8 bit-30 mhz-2ch 8 bit-30 mhz-3ch remark t a = ? 40 to + 85 c
ma-9 family 32 pamphlet a13326ej2v0pf ma-9 family development procedure the ma-9 family is developed by separating the logic circuit and analog circuit and combining the circuit diagram level interface and simulation level interface. development method system circuit design lsi circuit design circuit synthesis layout design es production [logic circuit] simulation level interface [analog circuit] circuit diagram level interface (user side) (nec electronics side)
ma-9 family 33 pamphlet a13326ej2v0pf logic circuit: simulation level interface analog circuit: circuit diagram level interface user nec electronics development support analog circuit interface analog circuit: circuit design, simulation analog circuit: placement and routing, core configuration analog circuit: test pattern preparation mask production, es production test and preparation of product ratings cs production mp production delivery cs evaluation test and verification of product ratings confirmation confirmation es evaluation logic circuit: floor plan, placement and routing preparation of test patterns logic circuit: logic design, simulation confirmation simulation result verification confirmation of provisional specifications system circuit design determination of desired system specifications circuit specification adjustment
ma-9 family 34 pamphlet a13326ej2v0pf ma-9 family development tools the ma-9 family provides development tools that support asic development by the user for each logic circuit and analog circuit separately. for the logic circuits, a simple design environment is enabled by using opencad, nec electronics' original cae tool, and for the analog circuits, the design environment is enabled by using a cae tool ideal for digital-analog integrated circuits. analog artist circuit diagram entry: composer tm simulator: spectre/verilog tm hdl layout editor: dle,virtuoso layout tester: diva test circuit analog-logic i/f test circuit logic circuit analog circuit designed by opencad (nec electronics' original cae tool) designed by analog artist tm (cae tool of cadence design systems) cb-9vx analog ip core
ma-9 family 35 pamphlet a13326ej2v0pf design flowchart system 1 system 2 mixed signal core adc core logic synthesis entire circuit netlist logicsim. floor plan, layout, etc. layout data test patterns circuit diagram entry logic circuit a/d mix simulator analog circuit mixed signal core layout design and testing test design mixed signal core test program netlist layout data analog array element layout data analog array design analog array cell placement and routing analog artist opencad
36 pamphlet a13326ej2v0pf package sop ssop qfp no. of pins 20 16 20 20 24 30 36 38 42 48 44 44 48 48 52 52 64 64 64 68 72 74 80 80 80 100 100 100 100 120 120 144 160 176 208 240 lead pitch (mm) 1.27 0.65 0.65 0.65 0.65 0.65 0.65 0.65 0.65 0.65 0.8 0.8 0.5 0.65 0.65 1.00 0.5 0.8 1.0 0.65 0.5 1.0 0.5 0.65 0.8 0.4 0.5 0.5 0.65 0.4 0.5 0.5 0.5 0.4 0.5 0.5 nominal size 7.62 mm (300) 5.72 mm (225) 5.72 mm (225) 7.62 mm (300) 7.62 mm (300) 7.62 mm (300) 7.62 mm (300) 7.62 mm (300) 9.53 mm (375) 9.53 mm (375) body size (mm) 10 ? 10 10 ? 10 7 ? 7 10 ? 10 10 ? 10 14 ? 14 10 ? 10 14 ? 14 14 ? 20 10 ? 14 10 ? 10 20 ? 20 12 ? 12 14 ? 14 14 ? 20 12 ? 12 14 ? 14 14 ? 14 14 ? 20 14 ? 14 20 ? 20 20 ? 20 24 ? 24 20 ? 20 28 ? 28 32 ? 32 main unit thickness (mm) 2.70 1.40 1.00 2.20 1.40 2.55 1.00 1.40 2.00 2.20 2.20 3.70 1.00 2.00 2.70 1.00 1.40 1.00 2.20 1.00 2.70 1.40 1.40 1.40 1.40 1.40 packages ma-8a the ma-8a supports various packages, enabling users to select the package type and optimum number of pins for their system and circuit scale (chip size). mold packages
packages 37 pamphlet a13326ej2v0pf package fpbga no. of pins 61 80 161 209 225 249 257 273 303 393 ball array 3 4 4 4 4 4 4 4 4 4-0-2 body size (mm) 6 ? 6 7 ? 7 10 ? 10 12 ? 12 13 ? 13 13 ? 13 14 ? 14 15 ? 15 16 ? 16 16 ? 16 production status note note note package fplga no. of pins 64 84 100 108 112 168 192 224 304 405 ball array 3 4 full full 4 4 4 4 4 4-0-2 body size (mm) 6 ? 6 7.5 ? 7.5 8 ? 7 7.5 ? 7.5 8 ? 8 11 ? 11 11 ? 11 13 ? 13 16 ? 16 16 ? 16 production status note note note under development remarks 1. fpbga: fine pitch ball grid array, fplga: fine pitch land grid array 2. : can be produced blank: in planning 3 development costs, including the board and sorting jig, will be charged for a csp. csp (chip size package)
packages 38 pamphlet a13326ej2v0pf note low-thermal-resistance type remark : can be used, : under development, : cannot be used, blank: under study note low-thermal-resistance type remark : can be used, : under development, : cannot be used, blank: under study package type no. of external lead resin dimensions pitch thickness pins (mm) (mm) (mm) qfp (fp) 100 14 ? 14 0.50 1.45 120 20 ? 20 0.50 2.70 144 20 ? 20 0.50 2.70 160 note 20 ? 20 0.50 2.70 176 note 24 ? 24 0.50 2.70 208 note 28 ? 28 0.50 3.20 240 note 32 ? 32 0.50 3.20 304 note 40 ? 40 0.50 3.20 tqfp 100 14 ? 14 0.50 1.00 step size b60 c02 c40 c78 d01 d26 d52 d90 e16 package type no. of external lead resin dimensions pitch thickness pins (mm) (mm) (mm) qfp (fp) 100 14 ? 14 0.50 1.45 120 20 ? 20 0.50 2.70 144 20 ? 20 0.50 2.70 160 note 20 ? 20 0.50 2.70 176 note 24 ? 24 0.50 2.70 208 note 28 ? 28 0.50 3.20 240 note 32 ? 32 0.50 3.20 304 note 40 ? 40 0.50 3.20 tqfp 100 14 ? 14 0.50 1.00 the ma-9 family supports various packages, enabling users to select the package type and optimum number of pins for their system and circuit scale (chip size). for packages other than qfp, contact nec electronics. ma-9 family step size e54 e80 f18 f44 f70 g08 g34 g72
39 pamphlet a13326ej2v0pf packages package type no. of external lead resin dimensions pitch thickness pins (mm) (mm) (mm) qfp (fp) 100 14 ? 14 0.50 1.45 120 20 ? 20 0.50 2.70 144 20 ? 20 0.50 2.70 160 note 20 ? 20 0.50 2.70 176 note 24 ? 24 0.50 2.70 208 note 28 ? 28 0.50 3.20 240 note 32 ? 32 0.50 3.20 304 note 40 ? 40 0.50 3.20 tqfp 100 14 ? 14 0.50 1.00 step size h10 h49 h87 j26 j51 k15 k92 note low-thermal-resistance type remark : can be used, : under development, : cannot be used, blank: under study
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41 pamphlet a13326ej2v0pf
42 pamphlet a13326ej2v0pf
eeprom, fpbga, and opencad are trademarks of nec electronics corporation. analog artist, composer, and verilog are trademarks of cadence design systems, inc. pamphlet a13326ej2v0pf these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of may, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such nec electronics products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact nec electronics sales representative in advance to determine nec electronics's willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11 43
document no. a13326ej2v0pf00 (2nd edition) date published june 2003 n cp(k) ? nec electronics corporation 1998 nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044-435-5111 http://www.necel.com/ [north america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. tel: 408-588-6000 800-366-9782 http://www.necelam.com/ nec electronics shanghai, ltd. 7th floor, hsbc tower, 101yin cheng east road, pudong new area, shanghai p.r. china p.c:200120 tel: 021-6841-1138 nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r. o. c. tel: 02-2719-2377 nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 [asia & oceania] nec electronics hong kong limited 12/f., cityplaza 4, 12 taikoo wan road, hong kong tel: 2886-9318 seoul branch 11f., samik lavied or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 for further information, please contact: [europe] nec electronics (europe) gmbh oberrather str. 4 40472 d ? sseldorf, germany tel: 0211-6503-01 http://www.ee.nec.de/ sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091-504-2787 succursale fran?aise 9, rue paul dautier, b.p. 52 78142 velizy-villacoublay c ? dex france tel: 01-3067-5800 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands boschdijk 187a 5612 hb eindhoven the netherlands tel: 040-2445845 tyskland filial p.o. box 134 18322 taeby, sweden tel: 08-6380820 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908-691-133 g03.4

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